14 search results - page 1 / 3 » A Performance Driven Layout Compaction Optimization Algorith... |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
This paper presents a direct performance-driven placement algorithm for analog integrated circuits. The performance speci cations directly drive the layout tools without intermedi...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...