505 search results - page 5 / 101 » A Performance and Power Co-optimization Approach for Modern ... |
PATMOS
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
ACSC
2008
IEEE
14 years 3 months ago
2008
IEEE
In the future, if we are to continue to expect improved application performance we will have to achieve it by exploiting course-grained hardware parallelism rather then simply rel...
CODES
2001
IEEE
14 years 5 days ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...