204 search results - page 6 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
ASAP
2008
IEEE
13 years 9 months ago
2008
IEEE
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
DATE
2003
IEEE
14 years 24 days ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Stream processing applications such as image signal processing demand high throughput. However, customers increasingly demand runtime flexibility in their designs, which cannot b...