33 search results - page 3 / 7 » A Power Minimization Technique for Arithmetic Circuits by Ce... |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
ISLPED
1999
ACM
13 years 11 months ago
1999
ACM
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...