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ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 4 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ICASSP
2009
IEEE
14 years 2 months ago
Robust cross-race gene expression analysis
This paper develops a Bayesian network (BN) predictor to profile cross-race gene expression data. Cross-race studies face more data variability than single-lab studies. Our desig...
Hsun-Hsien Chang, Marco Ramoni
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
DAC
2006
ACM
14 years 8 months ago
GreenBus: a generic interconnect fabric for transaction level modelling
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...
Wolfgang Klingauf, Robert Günzel, Oliver Brin...
IJON
2010
138views more  IJON 2010»
13 years 6 months ago
A dynamic Bayesian network to represent discrete duration models
Originally devoted to specific applications such as biology, medicine and demography, duration models are now widely used in economy, finance or reliability. Recent works in var...
Roland Donat, Philippe Leray, Laurent Bouillaut, P...