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» A Probabilistic Approach to Buffer Insertion
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DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 10 months ago
Dynamic Power Management Using Data Buffers
This paper presents a method to reduce energy consumption by inserting data buffers. The method determines whether power can be reduced by inserting a buffer between two component...
Le Cai, Yung-Hsiang Lu
ISPD
2003
ACM
88views Hardware» more  ISPD 2003»
14 years 8 days ago
Porosity aware buffered steiner tree construction
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
14 years 1 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
DAC
2006
ACM
14 years 8 months ago
Fast algorithms for slew constrained minimum cost buffering
As a prevalent constraint, sharp slew rate is often required in circuit design which causes a huge demand for buffering resources. This problem requires ultra-fast buffering techn...
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K...
ICCAD
2000
IEEE
102views Hardware» more  ICCAD 2000»
13 years 11 months ago
Provably Good Global Buffering Using an Available Buffer Block Plan
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...