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RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 19 days ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
ASPLOS
2006
ACM
14 years 1 months ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...
DT
2006
180views more  DT 2006»
13 years 7 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...
APAQS
2001
IEEE
13 years 11 months ago
Object-Oriented Program Behavior Analysis Based on Control Patterns
Code-patterns are statically recurring structure specific to a programming language. It can be parallel to aid in designing software systems for solving particular problems. Contr...
C.-C. Hwang, S.-K. Huang, D.-J. Chen, D. Chen
VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
14 years 7 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri