263 search results - page 18 / 53 » A Scalable Approach to Multi-style Architectural Modeling an... |
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
FLAIRS
2007
13 years 11 months ago
2007
This paper explores an inferential system for recognizing visual patterns. The system is inspired by a recent memoryprediction theory and models the high-level architecture of the...
SIGSOFT
2010
ACM
13 years 6 months ago
2010
ACM
Concurrent program verification is challenging because it involves exploring a large number of possible thread interleavings together with complex sequential reasoning. As a resul...
RTSS
2000
IEEE
14 years 1 months ago
2000
IEEE
The maturity of schedulabilty analysis techniquesfor fired-prioritypreemptive scheduling has enabled the consideration of timing issues at design time using a specification of the...
DAC
1996
ACM
14 years 22 days ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...