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IWPC
1996
IEEE
14 years 22 days ago
The Gadfly: An Approach to Architectural-Level System Comprehension
Technology to support system comprehension tends to reflect either a "bottom-up" or "top-down" approach. Bottom-up approaches attempt to derive system models f...
Kurt C. Wallnau, Paul C. Clements, Edwin J. Morris...
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 9 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
DAC
2006
ACM
14 years 9 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
14 years 2 months ago
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
Brad Matthews, Itamar Elhanany
FMSD
2008
110views more  FMSD 2008»
13 years 8 months ago
Automatic symbolic compositional verification by learning assumptions
Abstract Compositional reasoning aims to improve scalability of verification tools by reducing the original verification task into subproblems. The simplification is typically base...
Wonhong Nam, P. Madhusudan, Rajeev Alur