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» A Scalable Architecture for Montgomery Multiplication
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IPPS
2006
IEEE
14 years 1 months ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
CLUSTER
2009
IEEE
14 years 8 days ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 8 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
14 years 20 days ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...
CISIS
2010
IEEE
14 years 2 months ago
Scalability Analysis of Progressive Alignment on a Multicore
—Sequence alignment is a fundamental instrument in Bioinformatics. In recent years, numerous proposals have been addressing the problem of accelerating this class of applications...
Sebastian Isaza, Friman Sánchez, Georgi Gay...