30 search results - page 4 / 6 » A Scalable Instruction Queue Design Using Dependence Chains |
ISCA
2005
IEEE
14 years 28 days ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Allowing loads to issue out-of-order with respect to earlier unresolved store addresses is very important for extracting parallelism in large-window superscalar processors. Blindl...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...