Sciweavers

1234 search results - page 14 / 247
» A Scheduling and Pipelining Algorithm for Hardware Software ...
Sort
View
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
13 years 7 months ago
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
CODES
2003
IEEE
14 years 27 days ago
Synthesis of real-time embedded software with local and global deadlines
Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical pat...
Pao-Ann Hsiung, Cheng-Yi Lin
MICRO
2006
IEEE
74views Hardware» more  MICRO 2006»
14 years 1 months ago
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive...
Smruti R. Sarangi, Abhishek Tiwari, Josep Torrella...
BMCBI
2008
122views more  BMCBI 2008»
13 years 7 months ago
High-throughput bioinformatics with the Cyrille2 pipeline system
Background: Modern omics research involves the application of high-throughput technologies that generate vast volumes of data. These data need to be pre-processed, analyzed and in...
Mark W. E. J. Fiers, Ate van der Burgt, Erwin Date...
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 15 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...