1234 search results - page 50 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
CC
2007
Springer
14 years 1 months ago
2007
Springer
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
ITC
2000
IEEE
14 years 2 days ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded a...
INFOCOM
2000
IEEE
14 years 2 days ago
2000
IEEE
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...