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» A Self-Tuning Configurable Cache
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MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 10 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
MOBIDE
2003
ACM
13 years 12 months ago
Consistency mechanisms for a distributed lookup service supporting mobile applications
This paper presents a general-purpose distributed lookup service, denoted Passive Distributed Indexing (PDI). PDI stores entries in form of (key, value) pairs in index caches loca...
Christoph Lindemann, Oliver P. Waldhorst
JCP
2007
181views more  JCP 2007»
13 years 6 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 11 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
CNSM
2010
13 years 4 months ago
A performance view on DNSSEC migration
In July 2008, the Kaminsky attack showed that DNS is sensitive to cache poisoning, and DNSSEC is considered the long term solution to mitigate this attack. A lot of technical docum...
Daniel Migault, Cedric Girard, Maryline Laurent