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» A Simulation Based Study of TLB Performance
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ISCA
1992
IEEE
111views Hardware» more  ISCA 1992»
13 years 11 months ago
A Simulation Based Study of TLB Performance
J. Bradley Chen, Anita Borg, Norman P. Jouppi
ISCA
2002
IEEE
123views Hardware» more  ISCA 2002»
14 years 16 days ago
Going the Distance for TLB Prefetching: An Application-Driven Study
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
Gokul B. Kandiraju, Anand Sivasubramaniam
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
ICPP
2002
IEEE
14 years 16 days ago
Analysis of Memory Hierarchy Performance of Block Data Layout
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
Neungsoo Park, Bo Hong, Viktor K. Prasanna
HPCA
2001
IEEE
14 years 8 months ago
Reevaluating Online Superpage Promotion with Hardware Support
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. ...