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GLOBECOM
2008
IEEE
14 years 1 months ago
Optimal LLR Clipping Levels for Mixed Hard/Soft Output Detection
Abstract—Consider a communications system where the detector generates a mix of hard and soft outputs, which are then fed into a soft-input channel decoder. In such a setting, it...
Ernesto Zimmermann, David L. Milliner, John R. Bar...
DATE
2009
IEEE
143views Hardware» more  DATE 2009»
14 years 2 months ago
Dimensioning heterogeneous MPSoCs via parallelism analysis
—In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems...
Bastian Ristau, Torsten Limberg, Oliver Arnold, Ge...
DAC
1997
ACM
13 years 11 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider
VLSID
2003
IEEE
77views VLSI» more  VLSID 2003»
14 years 7 months ago
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
There is an increasing need for obtaining a reasonably accurate estimate of energy dissipation in SoC designs. Array structures have a significant contribution to the total system...
Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
ISCAS
2006
IEEE
129views Hardware» more  ISCAS 2006»
14 years 1 months ago
Computing during supply voltage switching in DVS enabled real-time processors
In recent times, much attention has been devoted to power optimization for real-time systems, while guaranteeing that such systems meet their hard (or soft) scheduling deadlines. ...
Chunjie Duan, Sunil P. Khatri