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» A Single-Path Chip-Multiprocessor System
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PPOPP
2005
ACM
14 years 1 months ago
Exposing speculative thread parallelism in SPEC2000
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...
Manohar K. Prabhu, Kunle Olukotun
ASPLOS
2009
ACM
14 years 8 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
HPCA
2007
IEEE
14 years 7 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 2 months ago
Coordinated control of multiple prefetchers in multi-core systems
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N....
IPPS
2006
IEEE
14 years 1 months ago
Helper thread prefetching for loosely-coupled multiprocessor systems
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihi...