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» A Spatial Logic for Concurrency
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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 4 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
SAC
2010
ACM
14 years 2 months ago
Dual analysis for proving safety and finding bugs
Program bugs remain a major challenge for software developers and various tools have been proposed to help with their localization and elimination. Most present-day tools are base...
Corneliu Popeea, Wei-Ngan Chin
PADS
2009
ACM
14 years 2 months ago
An Approach for Validation of Semantic Composability in Simulation Models
Semantic composability aims to ensure that the composition of simulation components is meaningful in terms of their expressed behavior, and achieves the desired objective of the n...
Claudia Szabo, Yong Meng Teo
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 2 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
IPPS
2000
IEEE
14 years 4 days ago
Deterministic Replay of Distributed Java Applications
Execution behavior of a Java application can be nondeterministic due to concurrent threads of execution, thread scheduling, and variable network delays. This nondeterminism in Jav...
Ravi B. Konuru, Harini Srinivasan, Jong-Deok Choi