340 search results - page 6 / 68 » A Statistical Performance Simulation Methodology for VLSI Ci... |
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
VLSI
2005
Springer
14 years 2 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
DAC
2004
ACM
14 years 9 days ago
2004
ACM
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
VLSID
2007
IEEE
14 years 2 months ago
2007
IEEE
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...