Abstract—Network flow models serve as a popular mathematical framework for the analysis and optimization of Multi-hop Wireless Networks. They also serve to provide the understan...
ct This paper provides an overview of the WarpIV Simulation Kernel that was designed to be an initial implementation of the Standard Simulation Architecture (SSA). WarpIV is the ne...
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...