Sciweavers

1675 search results - page 302 / 335
» A Structured Approach to Parallel Programming: Methodology a...
Sort
View
ICC
2009
IEEE
190views Communications» more  ICC 2009»
15 years 11 months ago
Decomposition for Low-Complexity Near-Optimal Routing in Multi-Hop Wireless Networks
Abstract—Network flow models serve as a popular mathematical framework for the analysis and optimization of Multi-hop Wireless Networks. They also serve to provide the understan...
Vinay Kolar, Nael B. Abu-Ghazaleh, Petri Mäh&...
PADS
2005
ACM
15 years 10 months ago
The WarpIV Simulation Kernel
ct This paper provides an overview of the WarpIV Simulation Kernel that was designed to be an initial implementation of the Standard Simulation Architecture (SSA). WarpIV is the ne...
Jeffrey S. Steinman
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
16 years 1 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
15 years 11 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
186
Voted
DAC
2010
ACM
15 years 8 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov