226 search results - page 4 / 46 » A Study on Impact of Leakage Current on Dynamic Power |
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper we propose a new metric called “effective tunneling capacitance” (Ct eff ) to quantify the transient swing in the gate leakage (gate oxide tunneling) current ...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...
ICCAD
2010
IEEE
13 years 1 months ago
2010
IEEE
Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper...