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ICES
2003
Springer
151views Hardware» more  ICES 2003»
14 years 1 months ago
Using Genetic Programming and High Level Synthesis to Design Optimized Datapath
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
Sérgio G. Araújo, Antônio C. M...
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 4 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
14 years 1 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
ICIP
2003
IEEE
14 years 9 months ago
A modular approach to virtual view creation for a scalable immersive teleconferencing configuration
This paper details a new modular approach to virtual view creation that is designed to work in conjunction with a proposed scalable teleconferencing configuration. This scalable s...
Eddie Cooke, Ingo Feldmann, Peter Kauff, Oliver Sc...
DAC
2004
ACM
14 years 8 months ago
Modular scheduling of guarded atomic actions
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods an...
Daniel L. Rosenband, Arvind