284 search results - page 22 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
LCTRTS
2001
Springer
14 years 8 days ago
2001
Springer
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
FPGA
1999
ACM
14 years 3 days ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...