284 search results - page 37 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
CEC
2007
IEEE
13 years 9 months ago
2007
IEEE
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
CODES
2009
IEEE
14 years 2 months ago
2009
IEEE
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
GLVLSI
2010
IEEE
14 years 27 days ago
2010
IEEE
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true ...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...