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TCAD
2010
121views more  TCAD 2010»
13 years 2 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
CODES
2003
IEEE
14 years 1 months ago
A low power scheduler using game theory
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
N. Ranganathan, Ashok K. Murugavel
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 12 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 4 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
HYBRID
1994
Springer
13 years 12 months ago
Symbolic Controller Synthesis for Discrete and Timed Systems
This paper presents algorithms for the symbolic synthesis of discrete and real-time controllers. At the semantic level the controller is synthesized by nding a winning strategy for...
Eugene Asarin, Oded Maler, Amir Pnueli