284 search results - page 7 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
ASYNC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylization...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...