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» A System Level Resource Estimation Tool for FPGAs
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WSC
2007
14 years 1 months ago
Simulation tool for manpower forecast loading and resource leveling
Large scale / mega projects are lengthy complex endeavors that require significant planning by management, engineers and construction personnel to ensure the success of the projec...
Mikhail Hanna, Janaka Y. Ruwanpura
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 3 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 4 months ago
Run-Time Management of Logic Resources on Reconfigurable Systems
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 4 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
ISSS
1997
IEEE
103views Hardware» more  ISSS 1997»
14 years 3 months ago
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
Chih-Tung Chen, Kayhan Küçük&cced...