209 search results - page 2 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
EURODAC
1990
IEEE
13 years 11 months ago
1990
IEEE
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
VLSID
1998
IEEE
13 years 12 months ago
1998
IEEE
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
ARVLSI
1999
IEEE
14 years 17 hour ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
WCE
2007
13 years 8 months ago
2007
Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniq...