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» A Systematic Approach for Designing Testable VLSI Circuits
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VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
14 years 8 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 12 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 4 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 1 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 4 months ago
Optimizing yield in global routing
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
Dirk Müller