Sciweavers

232 search results - page 36 / 47
» A Systematic Incrementalization Technique and Its Applicatio...
Sort
View
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 1 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
IPPS
2000
IEEE
13 years 11 months ago
Image Layer Decomposition for Distributed Real-Time Rendering on Clusters
We propose a novel work partitioning technique, Image Layer Decomposition (ILD), designed specifically to support distributed real-time rendering on commodity clusters. ILD has s...
Thu D. Nguyen, John Zahorjan
ERSA
2006
197views Hardware» more  ERSA 2006»
13 years 8 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney