452 search results - page 41 / 91 » A Systematic Process to Design Product Line Architecture |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
CCR
2002
13 years 7 months ago
2002
Economic principles are increasingly being suggested for addressing some complex issues related to distributed resource allocation for QoS (Quality of Service) enhancement. Many p...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
FPL
2009
Springer
14 years 14 days ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...