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DFT
2003
IEEE
117views VLSI» more  DFT 2003»
14 years 1 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
CHI
2001
ACM
14 years 8 months ago
Exploring 3D navigation: combining speed-coupled flying with orbiting
We present a task-based taxonomy of navigation techniques for 3D virtual environments, used to categorize existing techniques, drive exploration of the design space, and inspire n...
Desney S. Tan, George G. Robertson, Mary Czerwinsk...
VRST
2006
ACM
14 years 2 months ago
Intuitively specifying object dynamics in virtual environments using VR-WISE
Designing and building Virtual Environments is not an easy task, especially when it comes to specifying object behavior where either knowledge about animation techniques or progra...
Bram Pellens, Frederic Kleinermann, Olga De Troyer
ASAP
2007
IEEE
101views Hardware» more  ASAP 2007»
14 years 2 months ago
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754)....
Charles Tsen, Michael J. Schulte, Sonia Gonzalez-N...
CAI
2004
Springer
13 years 8 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
Lukás Sekanina, Stepan Friedl