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ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
14 years 2 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman
INTERACT
2007
13 years 9 months ago
CubeExplorer: An Evaluation of Interaction Techniques in Architectural Education
During the early stages of architectural training, tangibility plays an important role in developing spatial awareness. In such contexts, tangible user interfaces are believed to p...
Hyunyoung Song, François Guimbretièr...
DATE
2004
IEEE
149views Hardware» more  DATE 2004»
13 years 11 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede
CODES
2006
IEEE
13 years 11 months ago
Automatic phase detection for stochastic on-chip traffic generation
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
UIST
2009
ACM
14 years 2 months ago
Virtual shelves: interactions with orientation aware devices
Triggering shortcuts or actions on a mobile device often requires a long sequence of key presses. Because the functions of buttons are highly dependent on the current applicationâ...
Frank Chun Yat Li, David Dearman, Khai N. Truong