819 search results - page 57 / 164 » A Technique for Combined Virtual Prototyping and Hardware De... |
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
CONIELECOMP
2011
IEEE
12 years 11 months ago
2011
IEEE
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
ISCAS
1999
IEEE
14 years 10 days ago
1999
IEEE
High-level power design presents a complex, multiobjective problem that involves the simultaneous optimisation of competing criteria such as speed, area and power. It is difficult...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...