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» A Test Point Insertion Algorithm for Mixed-Signal Circuits
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DATE
2009
IEEE
93views Hardware» more  DATE 2009»
14 years 2 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...
TC
2010
13 years 5 months ago
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
DAC
2005
ACM
14 years 8 months ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
13 years 11 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 4 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt