264 search results - page 32 / 53 » A Time Predictable Instruction Cache for a Java Processor |
CASES
2007
ACM
14 years 19 days ago
2007
ACM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
IEEEPACT
2000
IEEE
14 years 1 months ago
2000
IEEE
Branch prediction accuracy is a very important factor for superscalarprocessor performance. The ability topredict the outcome of a branch allows the processor to effectively use a...
PLDI
2012
ACM
11 years 11 months ago
2012
ACM
We propose a new language-based approach to mitigating timing channels. In this language, well-typed programs provably leak only a bounded amount of information over time through ...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
DSN
2002
IEEE
14 years 1 months ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...