264 search results - page 38 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ASPLOS
2000
ACM
14 years 1 months ago
2000
ACM
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there ...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
VEE
2009
ACM
14 years 3 months ago
2009
ACM
Today’s web applications are pushing the limits of modern web browsers. The emergence of the browser as the platform of choice for rich client-side applications has shifted the ...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...