3955 search results - page 4 / 791 » A Transactional Architecture for Simulation |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
CSE
2009
IEEE
14 years 2 months ago
2009
IEEE
The evolution of wireless networks and mobile devices has resulted in increased concerns about performance and security of mobile payment systems. In this paper we propose SA2pMP,...
CIDR
2011
12 years 11 months ago
2011
Hyder supports reads and writes on indexed records within classical multi-step transactions. It is designed to run on a cluster of servers that have shared access to a large pool ...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...