81 search results - page 5 / 17 » A Variation Aware High Level Synthesis Framework |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
A leaf-level clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few high-end designs because of the high power/resource requirements and la...
TCAD
2010
13 years 2 months ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
ISSS
2002
IEEE
14 years 16 days ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...