81 search results - page 5 / 17 » A Variation Aware High Level Synthesis Framework |
ASPDAC
2008
ACM
15 years 5 months ago
2008
ACM
A leaf-level clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few high-end designs because of the high power/resource requirements and la...
132
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TCAD
2010
14 years 10 months ago
2010
Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clo...
108
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ISSS
2002
IEEE
15 years 8 months ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
116
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
112
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EURODAC
1994
IEEE
15 years 7 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...