466 search results - page 22 / 94 » A Worst Case Timing Analysis Technique for Optimized Program... |
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
ISVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
In nanometer regime, the effects of process variations are dominating circuit performance, power and reliability of circuits. Hence, it is important to properly manage variation e...
DAC
2006
ACM
14 years 2 months ago
2006
ACM
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
ASPDAC
2005
ACM
14 years 2 months ago
2005
ACM
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
ISPD
2010
ACM
14 years 3 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...