228 search results - page 19 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DSN
2005
IEEE
14 years 2 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
DAC
1996
ACM
14 years 22 days ago
1996
ACM
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
ATS
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...