228 search results - page 30 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
SPAA
2005
ACM
14 years 2 months ago
2005
ACM
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
ISCA
2008
IEEE
14 years 3 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
DAC
1994
ACM
14 years 22 days ago
1994
ACM
-- In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis...
FPGA
2005
ACM
14 years 2 months ago
2005
ACM
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...