228 search results - page 34 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DAC
2005
ACM
13 years 10 months ago
2005
ACM
We propose a hierarchical mixed signal design methodology based on the principles of Platform-Based Design (PBD). The methodology is a meet-in-the-middle approach where design com...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
ASYNC
2006
IEEE
14 years 2 months ago
2006
IEEE
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...