228 search results - page 35 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
ASPDAC
2007
ACM
14 years 19 days ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
AINA
2008
IEEE
14 years 3 months ago
2008
IEEE
—Network Intrusion Detection System (NIDS) is a system developed for identifying attacks by using a set of rules. NIDS is an efficient way to provide the security protection for ...
ESANN
2004
13 years 10 months ago
2004
: The architecture of a complete image segmentation system and the development of an embedded VLSI low-power integrated circuit are reported. A neuromorphic engineering approach is...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
TVLSI
1998
13 years 8 months ago
1998
—In most low-power VLSI designs, the supply voltage is usually reduced to lower the total power consumption. However, the device speed will be degraded as the supply voltage goes...