228 search results - page 5 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
GLVLSI
2010
IEEE
14 years 16 days ago
2010
IEEE
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
ISLPED
2009
ACM
14 years 1 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...