228 search results - page 8 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
ARVLSI
1995
IEEE
14 years 4 days ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
TVLSI
2010
13 years 3 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...