121 search results - page 11 / 25 » A cell-based power estimation in CMOS combinational circuits |
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
PATMOS
2004
Springer
14 years 25 days ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
ISMVL
2003
IEEE
14 years 23 days ago
2003
IEEE
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evalua...