121 search results - page 16 / 25 » A cell-based power estimation in CMOS combinational circuits |
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...