6 search results - page 1 / 2 » A clock delayed sleep mode domino logic for wide dynamic OR ... |
ISLPED
2003
ACM
14 years 3 months ago
2003
ACM
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
GLVLSI
2006
IEEE
14 years 3 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
GLVLSI
2003
IEEE
14 years 3 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...