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171
Voted
CODES
2005
IEEE
15 years 11 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
209
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CODES
2003
IEEE
15 years 10 months ago
2003
IEEE
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
155
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OSDI
2002
ACM
16 years 5 months ago
2002
ACM
This paper shows how to quickly move the state of a running computer across a network, including the state in its disks, memory, CPU registers, and I/O devices. We call this state...
212
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ISCA
2010
IEEE
15 years 10 months ago
2010
IEEE
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
176
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CODES
2008
IEEE
15 years 7 months ago
2008
IEEE
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...